1. Technical Field
The present invention relates to a voltage supply apparatus and method and, in particular, to a voltage supply apparatus and method for supplying a voltage to an operation circuit of a semiconductor memory apparatus.
2. Related Art
In general, as semiconductor memories become highly integrated, each element of a memory circuit has become smaller. A CPU (Central Processing Unit) used in a system having a semiconductor memory is designed to operate at a high frequency. Thus the semiconductor memory is also designed to operate at a high frequency.
In order to design a memory that operates at a high frequency, the power voltage of the semiconductor memory needs to be low. However, as the power voltage becomes low, noise may cause critical problems.
Currently, in a semiconductor memory apparatus, a plurality of power voltages applied from the outside at the same level is used. Further, a plurality of voltages generated within a chip from the power voltages is used and pads thereof are separated.
FIG. 1 is a circuit diagram showing a conventional voltage supplying apparatus.
The conventional voltage supplying apparatus includes: a first inverter IV1, a second inverter IV2, a PMOS transistor P1 and a NMOS transistor N1.
The first inverter IV1 receives a voltage supply enable signal EN_SIG, inverts the received voltage supply enable signal EN_SIG, and outputs the inverted voltage supply enable signal as an output signal EN_SIGb.
The second inverter IV2 inverts an output signal EN_SIGb of the first inverter IV1 and outputs the inverted output signal as an output signal EN_SIG.
The PMOS transistor P1 has a gate terminal that receives the output signal EN_SIGb of the first inverter IV1, a source terminal to which a power voltage VDDA or VDDB is applied, and a drain terminal that is connected to an operation circuit 10.
The NMOS transistor N1 has a gate terminal that receives the output signal EN_SIG of the second inverter IV2, a source terminal to which a ground voltage VSSA or VSSB is applied, and a drain terminal that is connected to the operation circuit 10.
The operation circuit 10 is a general circuit which receives the power voltage VDDA or VDDB or the ground voltage VSSA or VSSB and which outputs the output signal OUTPUT_ORG.
Here, the operation circuit 10 receives a first power voltage VDDA and a first ground voltage VSSA or receives a second power voltage VDDB and a second ground voltage VSSB.
As shown in FIG. 1, the conventional voltage supply apparatus is designed such that only a fixed power voltage is supplied in response to the voltage supply enable signal EN_SIG, which activates the voltage supply apparatus.
However, no circuit senses an amount of noise in the voltages applied to the memory, even when each power supply applied to the memory has a different amount of noise. That is, even when the amount of noise generated in the first power voltage VDDA and the first ground voltage VSSA is greater than the amount of noise generated in the second power voltage VDDB and the second ground voltage VSSB, the first power voltage VDDA and the first ground voltage VSSA are used.
As described above, since the conventional voltage supply apparatus cannot sense power noise, there is a problem in that the semiconductor memory may function erroneously due to the noise, thereby reducing the performance of the semiconductor memory.